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19-3281; Rev 1; 1/05
-48V Hot-Swap Controllers with VIN Step Immunity and No RSENSE
General Description
The MAX5936/MAX5937 are hot-swap controllers for -10V to -80V rails. The MAX5936/MAX5937 allow circuit line cards to be safely hot-plugged into a live backplane without causing a glitch on the power supply. These devices integrate a circuit-breaker function requiring no RSENSE. The MAX5936/MAX5937 provide a controlled turn-on for circuit cards, limiting inrush, preventing glitches on the power-supply rail, and preventing damage to board connectors and components. Before startup, the devices perform a Load ProbeTM test to detect the presence of a short-circuit condition. If a short-circuit condition does not exist, the device limits the inrush current drawn by the load by gradually turning on the external MOSFET. Once the external MOSFET is fully enhanced, the MAX5936/MAX5937 provides overcurrent and short-circuit protection by monitoring the voltage drop across the RDS(ON) of the external power MOSFET. The MAX5936/MAX5937 integrate a 400mA fast GATE pulldown to guarantee that the power MOSFET is rapidly turned off in the event of an overcurrent or short-circuit condition. The MAX5936/MAX5937 protect the system against input voltage (VIN) steps by providing VIN step immunity. The MAX5936/MAX5937 provide an accurate UVLO voltage. The MAX5936 has an open-drain, active-low PGOOD output and the MAX5937 has an open-drain, active-high PGOOD output. The MAX5936/MAX5937 are offered with 100mV, 200mV, and 400mV circuit-breaker thresholds, in addition to a non-circuit-breaker option. These devices are offered in latched and autoretry fault management, are available in 8-pin SO packages, and specified for the extended (-40C to +85C) temperature range (see the Selector Guide). o -10V to -80V Operation o No RSENSE Required o Drives Large Power MOSFETS o Programmable Inrush Current Limit During Hot Plug o 100mV, 200mV, 400mV, and No-Circuit-Breaker Threshold Options o Circuit-Breaker Fault with Transient Rejection o Shorted Load Detection (Load Probe) Before Power MOSFET Turn-On o 2.4% Accurate Undervoltage Lockout (UVLO) o Autoretry and Latched Fault Management Available o Low Quiescent Current
Features
MAX5936/MAX5937
Ordering Information
PART MAX5936_ _ESA MAX5937_ _ESA TEMP RANGE -40C to +85C -40C to +85C PIN-PACKAGE 8 SO 8 SO
Note: The first "_" represents A for the autoretry and L for the latched fault management option. The second "_" represents the circuit-breaker threshold. See the Selector Guide for additional information. Selector Guide and Typical Operating Circuit appear at end of data sheet.
Applications
Servers Telecom Line Cards Network Switches Solid-State Circuit Breaker Network Routers
UVLO 2 STEP_MON 3 GND 1
Pin Configuration
TOP VIEW
8 7
PGOOD (PGOOD) VOUT GATE LP
MAX5936 MAX5937
6 5
VEE 4
SO
Load Probe is a trademark of Maxim Integrated Products, Inc.
( ) FOR THE MAX5937.
________________________________________________________________ Maxim Integrated Products
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For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
-48V Hot-Swap Controllers with VIN Step Immunity and No RSENSE MAX5936/MAX5937
ABSOLUTE MAXIMUM RATINGS
VEE, VOUT, PGOOD (PGOOD), LP, STEP_MON to GND............................................+0.3V to -85V PGOOD (PGOOD) to VOUT ....................................-0.3V to +85V PGOOD (PGOOD), LP, STEP_MON to VEE ............-0.3V to +85V GATE to VEE ...........................................................-0.3V to +20V UVLO to VEE .............................................................-0.3V to +6V Input Current LP (internally, duty-cycle limited).........................................1A PGOOD (PGOOD) (continuous) .....................................80mA GATE (during 15V clamp, continuous) ...........................30mA GATE (during 2V clamp, continuous) .............................50mA GATE (during gate pulldown, continuous)......................50mA Continuous Power Dissipation (TA = +70C) 8-Pin SO (derate 5.9mW/C above +70C)..................471mW Operating Temperature Range ...........................-40C to +85C Junction Temperature .....................................................+150C Storage Temperature Range ............................-65C to +150C Lead Temperature (soldering, 10s) ................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VEE = -10V to -80V, VIN = GND - VEE, VSTEP_MON = VEE, RLP = 200, UVLO open, TA = -40C to +85C, unless otherwise noted. Typical values are at VEE = -48V, TA = +25C.) (Notes 1, 2)
PARAMETER Operating Voltage Range Operating Supply Current Default VEE Undervoltage Lockout UVLO Reference Threshold, VEE Rising UVLO Reference Threshold, VEE Falling UVLO Input Resistance UVLO Transient Rejection Power-Up Delay (Note 3) VEE and UVLO Glitch Rejection (Note 4) VOUT to VEE Leakage Current LP to VEE Leakage Current External Gate-Drive Voltage VGS tOVREJ tONDLY tREJ VEE = -80V, VOUT = GND VEE = -80V, VLP = GND VGATE - VEE MOSFET fully enhanced GATE to VEE Clamp Voltage Power-off, VEE = GND VGATE - VEE = 500mV l dVOUT/dt l VIN = 10V 14 VIN 80V ICLAMP = 9mA ICLAMP = 20mA ICLAMP = 1mA ICLAMP = 10mA -66 VIN > 10V VIN > 14V 2.4 6.5 8.1 13.5 SYMBOL VEE ICC VUVLO,R VUVLO,F VUVLO_REF,R VUVLO_REF,F lVEEl increasing lVEEl decreasing VUVLO increasing VUVLO decreasing 1.219 1.069 20 0.8 80 0.8 1.5 220 1.5 0.01 0.01 6.8 10 16 17 2.1 2.5 -52 9 7.5 9 19.5 2.55 2.9 -35 14.1 12.5 14.8 A V/ms V -33.5 CONDITIONS Referenced to GND MIN -80 0.95 -31.0 -28 1.25 1.125 1.281 1.181 50 2.25 380 2.25 1 1 7.2 12.8 TYP MAX -10 1.4 -29.5 UNITS V mA V V V k ms ms ms A A V
Open-Loop Gate-Charge Current GATE Pulldown Switch On-Resistance Output-Voltage Slew Rate RGATE SR
VGATE = VEE, VOUT = GND
2
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-48V Hot-Swap Controllers with VIN Step Immunity and No RSENSE
ELECTRICAL CHARACTERISTICS (continued)
(VEE = -10V to -80V, VIN = GND - VEE, VSTEP_MON = VEE, RLP = 200, UVLO open, TA = -40C to +85C, unless otherwise noted. Typical values are at VEE = -48V, TA = +25C.) (Notes 1, 2)
PARAMETER Circuit-Breaker Tempco Circuit-Breaker Glitch Rejection tCB_DLY MAX5936LA/ MAX5936AA/ MAX5937LA/ MAX5937AA MAX5936LB/ MAX5936AB/ MAX5937LB/ MAX5937AB MAX5936LC/ MAX5936AC/ MAX5937LC/ MAX5937AC MAX5936LA/ MAX5936AA/ MAX5937LA/ MAX5937AA MAX5936LB/ MAX5936AB/ MAX5937LB/ MAX5937AB MAX5936LC/ MAX5936AC/ MAX5937LC/ MAX5937AC Short-Circuit Response Time (Note 5) INPUT-VOLTAGE-STEP PROTECTION Input-Voltage-Step Detection Threshold Input-Voltage-Step Threshold Offset Current LOAD-PROBE CIRCUIT Load-Probe Switch On-Resistance Load-Probe Timeout Load-Probe Retry Time Load-Probe Voltage Threshold tLP tLP_OFF VTHSC-DET Referenced to GND -220 VLP - VEE = 1V 80 7.5 220 16 x tLP -200 -180 11 380 ms s mV STEPTH ISTEP_OS 1.219 -10.8 1.250 -10.0 1.281 -9.2 V A TA = +85C TA = +25C TA = -10C TA = -40C TA = +85C TA = +25C TA = -10C TA = -40C TA = +85C TA = +25C TA = -10C TA = -40C TA = +85C TA = +25C TA = -10C TA = -40C TA = +85C TA = +25C TA = -10C TA = -40C TA = +85C TA = +25C TA = -10C TA = -40C 962 700 510 470 350 255 220 160 111 485 355 270 244 180 135 SYMBOL CONDITIONS -40C < TA <+85C 1.0 118 85 64 MIN TYP 6000 1.2 140 100 79 62 284 200 158 124 568 400 316 248 280 200 158 124 568 400 316 248 1136 800 632 496 330 500 ns 1310 900 754 667 450 377 mV 340 240 205 651 445 362 324 220 181 mV 1.6 162 115 94 MAX UNITS ppm/C ms
MAX5936/MAX5937
Circuit-Breaker Threshold
VCB
Short-Circuit Threshold
VSC
150mV overdrive, CLOAD = 0, to GATE below 1V
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-48V Hot-Swap Controllers with VIN Step Immunity and No RSENSE MAX5936/MAX5937
ELECTRICAL CHARACTERISTICS (continued)
(VEE = -10V to -80V, VIN = GND - VEE, VSTEP_MON = VEE, RLP = 200, UVLO open, TA = -40C to +85C, unless otherwise noted. Typical values are at VEE = -48V, TA = +25C.) (Notes 1, 2)
PARAMETER LOGIC AND FAULT MANAGEMENT Autoretry Delay tRETRY |VOUT - VEE| falling Hysteresis 0.67 VOL IL ISINK = 1mA, referenced to VOUT, VOUT < GND - 5V for PGOOD (PGOOD) VEE = -80V, VPGOOD(PGOOD), VPGOOD(PGOOD) = GND 16 x tLP 0.74 x VCB 0.26 x VCB 1.26 0.05 0.01 1.85 0.4 1 s SYMBOL CONDITIONS MIN TYP MAX UNITS
PGOOD (PGOOD) Assertion Threshold PGOOD (PGOOD) Assertion Delay Time (Note 6) PGOOD (PGOOD) Low Voltage PGOOD (PGOOD) Open-Drain Leakage
mV
ms V A
Note 1: All currents into pins are positive and all currents out of pins are negative. All voltages referenced to VEE, unless otherwise specified. Note 2: All limits are 100% tested at +25C and +85C. Limits at -40C and -10C are guaranteed by characterization. Note 3: Delay time from a valid on-condition until the load probe test begins. Note 4: VEE or UVLO voltages below VUVLO,F or VUVLO_REF,F, respectively, are ignored during this time. Note 5: The time (VOUT - VEE) > VSC + overdrive until (VGATE - VEE) drops to approximately 90% of its initial high value. Note 6: The time when the PGOOD (PGOOD) condition is met until the PGOOD (PGOOD) signal is asserted.
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-48V Hot-Swap Controllers with VIN Step Immunity and No RSENSE MAX5936/MAX5937
Typical Operating Characteristics
(VEE = -48V, GND = 0V, VIN = GND - VEE, all voltages are referenced to VEE, TA = +25C, unless otherwise noted.)
SUPPLY CURRENT vs. INPUT VOLTAGE
MAZ5936 toc01
SUPPLY CURRENT vs. TEMPERATURE
MAX5936 toc02
GATE-DRIVE VOLTAGE vs. INPUT VOLTAGE
10.0 GATE-DRIVE VOLTAGE (V) 9.5 9.0 8.5 8.0 7.5 7.0
MAX5936 toc03
2.0 1.8 1.6 SUPPLY CURRENT (mA) 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 10 20 30 40 50 60 70
1.2 1.0 SUPPLY CURRENT (mA)
VIN = 72V
10.5
VIN = 48V 0.8 0.6 0.4 0.2 VIN = 12V
6.5 0 80 -40 -15 10 35 60 85 INPUT VOLTAGE (V) TEMPERATURE (C) 6.0 10 20 30 40 50 60 70 80 INPUT VOLTAGE (V)
GATE PULLDOWN CURRENT vs. GATE VOLTAGE
MAX5936 toc04
RETRY TIME vs. TEMPERATURE
3.9 3.8 RETRY TIME (s) 3.7 3.6 3.5 3.4 3.3 3.2 3.1 3.0 CGATE = 0, CLOAD = 100F
MAX5936 toc05
500 450 GATE PULLDOWN CURRENT (mA) 400 350 300 250 200 150 100 50 0 0 1 2 3 4 5 6 7 8 9
4.0
10
-40
-15
10
35
60
85
VGATE (V)
TEMPERATURE (C)
STARTUP WAVEFORM
MAX5936 toc06
MAX5936_A CIRCUIT-BREAKER EVENT
MAX5936 toc07
VIN 50V/div VGATE 10V/div VOUT 50V/div VPGOOD 50V/div
VGATE 10V/div
VOUT 50V/div
VPGOOD 50V/div IIN 2A/div 1ms/div
IIN 2A/div 40ms/div
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-48V Hot-Swap Controllers with VIN Step Immunity and No RSENSE MAX5936/MAX5937
Typical Operating Characteristics (continued)
(VEE = -48V, GND = 0V, VIN = GND - VEE, all voltages are referenced to VEE, TA = +25C, unless otherwise noted.)
MAX5936_A SHORT-CIRCUIT EVENT
NORMALIZED CIRCUIT-BREAKER THRESHOLD (%)
MAX5936 toc08
NORMALIZED CIRCUIT-BREAKER THRESHOLD vs. TEMPERATURE
MAX5936 toc09
VOUT SLEW RATE vs. TEMPERATURE
9.5 9.0 SLEW RATE (V/ms) 8.5 8.0 7.5 7.0 6.5 6.0 5.5 VIN = 12V VIN = 48V CGATE = 0, CLOAD = 100F VIN = 72V
MAX5936 toc10
1.6 1.4 1.2 1.0 0.8 0.6 0.4 -40 -15 10 35 60
10.0
VGATE 10V/div
VOUT 50V/div VPGOOD 50V/div
IIN 10A/div 400ns/div
5.0 85 -40 -15 10 35 60 85 TEMPERATURE (C) TEMPERATURE (C)
MAX5936_A INPUT VOLTAGE STEP EVENT (NO FAULT)
MAX5936 toc11
MAX5936_A INPUT VOLTAGE STEP EVENT (FAULT)
MAX5936 toc12
RLOAD = 75
VIN 50V/div VGATE 10V/div VOUT 50V/div VPGOOD 50V/div IIN 1A/div 4ms/div
RLOAD = 75
VIN 50V/div VGATE 10V/div VOUT 50V/div VPGOOD 50V/div IIN 2A/div 4ms/div
GATE TO VEE CLAMP VOLTAGE AT POWER OFF
MAX5936 toc13
GATE TO VEE CLAMP VOLTAGE MOSFET FULLY ENHANCED
17 GATE CLAMPING VOLTAGE (V) 16 15 14 13 12 11 10 9 VEE = -48V, VUVLO = 2V
MAX5936 toc14
3.0 2.5 2.0 1.5 1.0 0.5 0 0
18
VEE = GND = 0V
GATE CLAMPING VOLTAGE (V)
8 2 4 6 8 10 12 14 16 18 20 0 2 4 6 8 10 12 14 16 18 20 ISINK (mA) ISINK (mA)
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-48V Hot-Swap Controllers with VIN Step Immunity and No RSENSE
Pin Description
PIN NAME MAX5936 1 MAX5937 1 GND Ground. The high-supply connection for a negative-rail hot-swap controller. Undervoltage Lockout Input, On/Off Control. Referenced to VEE. Drive UVLO above the 1.25V rising threshold to turn on the device. To turn off the device, drive UVLO below the 1.125V falling threshold for the 1.5ms glitch rejection period. Leave UVLO disconnected for the default 31V undervoltage lockout threshold. Cycle UVLO to unlatch the MAX5936L/ MAX5937L after a fault. Cycling UVLO low deasserts PGOOD. Input Voltage Step Monitor. 1.25V voltage threshold referenced to VEE. Connect a resistor between STEP_MON and VEE to set the step sensitivity. Connect a capacitor from GND to STEP_MON to adjust the step response relative to a step increase at VEE to eliminate false circuit-breaker and short-circuit faults. Connect to VEE to disable the step immunity function (see the Selecting Resistor and Capacitor Values for Step Monitor section in the Applications Information). Negative Input Voltage Load-Probe Detect. Connect a resistor from LP to VOUT to set the load-probe test current. Limit load-probe test current to 1A. Connect to VEE to disable the load-probe function. Gate-Drive Output. Connect to the gate of the external n-channel MOSFET. Output Voltage Sense. VOUT is the negative rail of the load. Connect to the drain of the external n-channel MOSFET. Power-Good, Active-Low, Open-Drain Output. Referenced to VOUT. PGOOD asserts low when VOUT is within the limits and there is no fault. Power-Good, Active-High, Open-Drain Output. Referenced to VOUT. PGOOD asserts high when VOUT is within limits and there is no fault. FUNCTION
MAX5936/MAX5937
2
2
UVLO
3
3
STEP_MON
4 5 6 7 8 --
4 5 6 7 -- 8
VEE LP GATE VOUT PGOOD PGOOD
Detailed Description
The MAX5936/MAX5937 hot-swap controllers incorporate overcurrent fault management and are intended for negative-supply-rail applications. The MAX5936/ MAX5937 eliminate the need for an external R SENSE and include VIN input-step protection and load probe, which prevents powering up into a shorted load. They are intended for negative 48V telecom power systems where low cost, flexibility, multifault management, and compact size are required. The MAX5936/MAX5937 are ideal for the widest range of systems from those requiring low current with small MOSFETs to highcurrent systems requiring large power MOSFETs and low on-resistance. The MAX5936/MAX5937 control an external n-channel power MOSFET placed in the negative supply path of an external load. When no power is applied, the GATE output of the MAX5936/MAX5937 clamps the VGS of the MOSFET to 2V, keeping the MOSFET turned off. When power is applied to the MAX5936/MAX5937, the 2V
clamp at the GATE output is replaced by a strong pulldown device pulling GATE to VEE and the VGS of the MOSFET to 0V. As shown in Figure 2, this transition enables the MAX5936/MAX5937 to keep the power MOSFET continually off during the board insertion phase when the circuit board first makes contact with the backplane. Without this clamp, the GATE output of a powered-down controller would be floating and the MOSFET reverse transfer capacitance (gate-to-drain) would pull up and turn on the MOSFET gate when the MOSFET drain is rapidly pulled up by the VIN step during backplane contact. The MAX5936/MAX5937 GATE clamp can overcome the gate-to-drain capacitance of large power MOSFETs with added slew-rate control (CSLEW) capacitors while eliminating the need for additional gate-to-source capacitance. The MAX5936/ MAX5937 will keep the MOSFET off indefinitely if the supply voltage is below the user-set UVLO threshold or if a short circuit is detected in the load connected to the drain of the power MOSFET.
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-48V Hot-Swap Controllers with VIN Step Immunity and No RSENSE MAX5936/MAX5937
GND RLOAD CLOAD
PGOOD PGOOD GND PGOOD PGOOD LOGIC VOUT 10V REG AND 5V REG +10V +5V VSC, VCB, AND 75% OF VCB COMPARATORS TEMPERATURECOMPENSATED CURRENT SOURCE
MAX5936 MAX5937
BANDGAP REF
VBG (1.25V)
UVLO
UVLO LOGIC CONTROL STEP 10A
FAULT DETECTION
52A
2V AND 15V CLAMP
GATE CONTROL GATE STEP_MON SEQUENCER CONTROLLER TIMER LP LOAD PROBE TEST VEE
VBG
VEE
Figure 1. Functional Block Diagram
The MAX5936/MAX5937 conduct a load-probe test after contact transients from the hot plug-in have settled. This follows the MAX5936/MAX5937 power-up (when the UVLO condition has been met for 220ms (tLP)) and prior to the turn-on of the power MOSFET. This test pulls a user-programmable current through the load (1A, max) for up to 220ms and tests for a voltage of 200mV across the load at VOUT. This current is set by an external resistor, RLP, between VOUT and LP (Figure 14). When the voltage across the load exceeds 200mV, the test is truncated and the GATE turn-on sequence is started. If at the end of the 220ms test period the voltage across the load has not reached 200mV, the load is assumed to be shorted and the current to the load from the LP pin is shut off. The MAX5936A_/MAX5937A_ will timeout for 16 x tLP then retry the load-probe test. The MAX5936L_/ MAX5937L_ will latch the fault condition indefinitely until
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the UVLO is brought below 1.125V for 1.5ms or the power is recycled. See the Applications Information section for recommendations on selecting RLP to set the current level. Upon successful completion of the load-probe test, the MAX5936/MAX5937 enter the power-up GATE cycle and begin ramping the GATE voltage with a 52A current source. This current source is restricted if VOUT begins to ramp down faster than the default 9V/ms slew rate. Charging up GATE enhances the power MOSFET in a controlled manner and ramping VOUT at a user-settable rate controls the inrush current from the backplane. The MAX5936/MAX5937 continue to charge up the GATE until one of two events occurs: a normal power-up GATE cycle is completed or a power-up to fault management is detected (see the GATE Cycles section in Appendix A).
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-48V Hot-Swap Controllers with VIN Step Immunity and No RSENSE MAX5936/MAX5937
CIN = 100F ALL VOLTAGES REFERENCED TO GND VEE 20V/div VIN 20V/div VLP 20V/div VGATE 1V/div
VOUT 20V/div 40ms/div
4ms/div
Figure 2. GATE Voltage Clamp During Power-Up
Figure 3. Load Probe Test During Initial Power-Up
In a normal power-up GATE cycle, the voltage at VOUT (referenced to VEE) ramps to below 74% of the circuitbreaker threshold voltage, VCB. At this time, the remaining GATE voltage is rapidly pulled up to full enhancement. PGOOD is asserted 1.26ms after GATE is fully enhanced (see Figure 4). If the voltage at VOUT remains above 74% of the VCB (when GATE reaches 90% of full enhancement), then a power-up to fault management fault has occurred (see Figure 5). GATE is rapidly pulled to VEE, turning off the power MOSFET and disconnecting the load. PGOOD remains deasserted and the MAX5936/ MAX5937 enter the fault management mode. When the power MOSFET is fully enhanced, the MAX5936/MAX5937 monitor the drain voltage (VOUT) for circuit-breaker and short-circuit faults. The MAX5936/ MAX5937 make use of the power MOSFET's RDS(ON) as the current-sense resistance to detect excessive current
through the load. The short-circuit threshold voltage, VSC, is twice VCB (VSC = 2 x VCB) and is available in 100mV, 200mV, and 400mV thresholds. VCB and VSC are temperature-compensated (increasing with temperature) to track the normalized temperature coefficient of RDS(ON) for typical power MOSFETs. When the load current is increased during full enhancement, this causes VOUT to exceed VCB but remains less than VSC, and starts the 1.2ms circuit-breaker glitch rejection timer. At the end of the glitch rejection period, if VOUT still exceeds VCB, the GATE is immediately pulled to VEE (330ns), PGOOD (PGOOD) is deasserted, and the part enters fault management. Alternatively, during full enhancement when V OUT exceeds V SC , there is no glitch rejection timer. GATE is immediately pulled to V EE , PGOOD is deasserted, and the part enters fault management.
VIN 50V/div VGATE 10V/div VOUT 50V/div
VIN 50V/div VGATE 10V/div VOUT 50V/div
VPGOOD 50V/div
VPGOOD 50V/div
IIN 2A/div 40ms/div 40ms/div
IIN 2A/div
Figure 4. MAX5936 Normal Condition
Figure 5. MAX5936 Startup in Fault Condition 9
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-48V Hot-Swap Controllers with VIN Step Immunity and No RSENSE
The VIN step immunity provides a means for transitioning through a large step increase in VIN with minimal backplane inrush current and without shutting down the load. Without VIN step immunity (when the power MOSFET is fully enhanced), a step increase in VIN will result in a high inrush current and a large step in VOUT, which can trip the circuit breaker. With VIN step immunity, the STEP_MON input detects the step before a short circuit is detected at V OUT and alters the MAX5936/MAX5937 response to V OUT exceeding VSC due to the step. The 1.25V voltage threshold at STEP_MON and a 10A current source at STEP_MON allow the user to set the sensitivity of the step detection with an external resistor to VEE. A capacitor is placed between GND and the STEP_MON input, which, in conjunction with the resistor, sets the STEP_MON time constant. When a step is detected by the STEP_MON input to rise above its threshold (STEPTH), the overcurrent fault management is blocked and remains blocked as long as STEPTH is exceeded. When STEPTH is exceeded, the MAX5936/MAX5937 take no action until VOUT rises above VSC or above VCB for the 1.2ms circuitbreaker glitch rejection period. When either of these conditions occurs, a step GATE cycle begins and the GATE is immediately brought to VEE, which turns off the power MOSFET to minimize the resulting inrush current surge from the backplane and PGOOD remains asserted. GATE is held at VEE for 350s, and after about 1ms, begins to ramp up thereby enhancing the power MOSFET in a controlled manner as in the power-up GATE cycle. This provides a controlled inrush current to charge the load capacitance to the new supply voltage (see the GATE Cycles section in Appendix A). As in the case of the power-up GATE cycle, if VOUT drops to less than 74% of the programmed VCB, independent of the state of STEP_MON, the GATE voltage
MAX5936/MAX5937
is rapidly pulled to full enhancement. PGOOD remains asserted throughout the step. Otherwise, if the STEP_MON input has decayed below its threshold but V OUT remains above 74% of the programmed V CB (when GATE reaches 90% of full enhancement), (a step-to-fault management fault has occurred). GATE is rapidly pulled to VEE, turning off the power MOSFET and disconnecting the load, PGOOD (PGOOD) is deasserted, and the MAX5936/MAX5937 enter the fault management mode.
Fault Management
Fault management can be triggered by the following conditions: * VOUT exceeds 74% of VCB during GATE ramp at 90% of full enhancement, * VOUT exceeds the VCB for longer than 1.2ms during full enhancement, * VOUT exceeds the VSC during full enhancement, and * Load-probe test fails. Once in the fault management mode, GATE will always be pulled to VEE to turn off the external MOSFET and PGOOD (PGOOD) will always be deasserted. The MAX5936A_/MAX5937A_ have automatic retry following a fault while the MAX5936L_/MAX5937L remain latched in the fault condition.
Autoretry Fault Management (MAX5936A_/MAX5937A_)
If the MAX5936A_/MAX5937A_entered fault management due to circuit-breaker and short-circuit faults, the autoretry timer starts immediately. The timer times out in 3.5s (typ) and at the end of the timeout, the sequencer initiates a load-probe test. If this is successful, it starts a normal power-up GATE cycle.
VIN 5V/div 40V VGATE 10V/div VOUT 20V/div VPGOOD 20V/div IIN 1A/div
40V 20V
VIN 20V/div VGATE 10V/div VOUT 50V/div VPGOOD 50V/div CLOAD = 100F RLOAD = 20 4ms/div IIN 5A/div
CLOAD = 100F RLOAD = 100 2ms/div
Figure 6. MAX5936 Response to a Step Input (VOUT < 0.74VCB) 10
Figure 7. MAX5936 Response to a Step Input (VOUT > 0.74VCB)
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-48V Hot-Swap Controllers with VIN Step Immunity and No RSENSE
Latched Fault Management (MAX5936L_/MAX5937L_)
When the MAX5936L_/MAX5937L_ enter fault management, they remain in this condition indefinitely until the power is recycled or until UVLO is brought below 1.125V for 1.5ms (typ) (when the short-circuit or circuitbreaker fault has cleared, the sequencer initiates a loadprobe test). If this is successful, it starts a normal power-up GATE cycle. A manual reset circuit (Figure 8) can be used to clear the latch. The short-circuit and circuit-breaker voltages are sensed at VOUT, which is the drain of the power MOSFET. The R DS(ON) of the MOSFET is the current-sense resistance, so the total current through the load and load capacitance is the drain current of the power MOSFET. Accordingly, the voltage at V OUT as a function of MOSFET drain current is: VOUT = ID,MOSFET x RDS(ON) The temperature compensation of the MAX5936/ MAX5937 is designed to track the RDS(ON) of the typical power MOSFET. Figure 9 shows the typical normalized tempco of the circuit-breaker threshold along with the normalized tempco of RDS(ON) for two typical power MOSFETS. When determining the circuit-breaker threshold in an application, go to the data sheet of the power MOSFET and locate the manufacturer's maximum RDS(ON) at +25C with a VGS of 10V. Next, find the figure presenting the tempco of normalized RDS(ON) or on-resistance vs. temperature. Because this curve is in normalized units typically with a value of 1 at +25C, it is possible to multiply the curve by the drain voltage at +25C and convert the curve to drain voltage. Now compare this curve to that of the MAX5936/MAX5937 normalized tempco of the circuit-breaker threshold to make a determination of the tracking error in mV between the power MOSFET [I D,MOSFET x RDS(ON)] and the MAX5936/MAX5937 over the application's operating temperature range. If the tempco of the power MOSFET is greater than that of the MAX5936/ MAX5937, then additional margin will be required in selecting the circuit-breaker and short-circuit voltages at higher temperatures as compared to +25C. When dissipation in the power MOSFET is expected to lead to local temperature elevation relative to ambient conditions, then it becomes imperative that the MAX5936/ MAX5937 be located as close as possible to the power MOSFET. The marginal effect of temperature differences on circuit-breaker and short-circuit voltages can be estimated from a comparative plot such as Figure 9.
MAX5936/MAX5937
Circuit-Breaker Thresholds
The MAX5936/MAX5937 are available with 100mV, 200mV, and 400mV circuit-breaker thresholds. The short-circuit voltage threshold (VSC) is twice the circuitbreaker threshold voltage (V CB ). In the MAX5936/ MAX5937, VCB and VSC are temperature-compensated (increasing with temperature) to track the normalized temperature gradient of typical power MOSFETs. The proper circuit-breaker threshold for an application depends on the RDS(ON) of the external power MOSFET and the maximum current the load is expected to draw. To avoid false fault indication and dropping of the load, the designer must take into account the load response to voltage ripples and noise from the backplane power supply, as well as switching currents in the downstream DC-DC converter that is loading the circuit. While the circuit-breaker threshold has glitch rejection that ignores ripples and noise lasting less than 1.2ms, the short-circuit detection is designed to respond very quickly (less than 330ns) to a short circuit. VSC and VCB must be selected from the three available ranges with an adequate margin to cover all possible ripples, noise, and system current transients.
VIN = (GND - VEE) GND R2
MAX5936LN and MAX5937LN
MAX5936L MAX5937L
UVLO R1 VEE
The MAX5936LN and MAX5937LN do not have circuitbreaker and short-circuit thresholds and these faults are ignored. For these devices PGOOD (PGOOD) asserts 1.26ms after GATE has ramped to 90% of full enhancement. The step detection function of the MAX5936LN and MAX5937LN responds to V IN and VOUT steps with the same voltage thresholds as the MAX5936_C and MAX5937_C.
Figure 8. Resetting MAX5936L/MAX5937L after a Fault Condition Using a Push-Button Switch ______________________________________________________________________________________ 11
-48V Hot-Swap Controllers with VIN Step Immunity and No RSENSE
NORMALIZED MOSFET ON-RESISTANCE vs. TEMPERATURE
1.6 NORMALIZED MOSFET ON-RESISTANCE 1.4 1.2 1.0 0.8 0.6 0.4 -40 MAX5936/MAX5937 NORMALIZED VCB IRFR3910 NORMALIZED RON IRF1310NS NORMALIZED RON -15 10 35 60 85
TEMPERATURE (C)
Figure 9. MAX5936/MAX5937 Normalized Circuit-Breaker Threshold (VCB)
PGOOD (PGOOD) Open-Drain Output
The power-good outputs, PGOOD (PGOOD), are open drain and are referenced to VOUT. They assert and latch if VOUT ramps below 72% of VCB, and with the built-in delay this occurs 1.26ms after the external MOSFET becomes fully enhanced. PGOOD (PGOOD) deasserts any time the part enters fault management. PGOOD (PGOOD) has a delayed response to UVLO. The GATE goes to VEE when UVLO is brought below 1.125V for 1.5ms. This turns off the power MOSFET and allows VOUT to rise depending on the RC time constant of the load. PGOOD (PGOOD), in this situation, deasserts when VOUT rises above VCB for more than 1.4ms or above VSC, whichever occurs first (see Figure 12b).
Due to the open-drain driver, PGOOD (PGOOD) requires an external pullup resistor to GND. Due to this external pullup, PGOOD will not follow positive VIN steps as well as if it were driven by an active pullup. As a result, when PGOOD (PGOOD) is asserted high, an apparent negative glitch appears at PGOOD (PGOOD) during a positive V IN step. This negative glitch is a result of the RC time constant of the external resistor and the PGOOD pin capacitance lagging the VIN step. It is not due to switching of the internal logic. To minimize this negative transient, it may be necessary to increase the pullup current and/or to add a small amount of capacitance from PGOOD (PGOOD) to GND to compensate for the pin capacitance. WARNING: For the MAX5936_N/MAX5937_N, PGOOD (PGOOD) asserts 1.26ms after the power MOSFET is fully enhanced, independent of VOUT. Once the MOSFET is fully enhanced and UVLO is pulled below its respective threshold, GATE pulls to V EE to turn off the power MOSFET and disconnect the load. When UVLO is cycled low, PGOOD (PGOOD) is deasserted. In summary, once the MOSFET is fully enhanced, the MAX5936_N/ MAX5937_N ignore VOUT and deassert PGOOD (PGOOD) when UVLO goes low or when the power to the MAX5936_N/ MAX5937_N is fully recycled.
MAX5936/MAX5937
Undervoltage Lockout (UVLO)
UVLO provides an accurate means to set the turn-on voltage level for the MAX5936/MAX5937. Use a resistordivider network from GND to V EE to set the desired turn-on voltage (Figure 11). UVLO has hysteresis with a rising threshold of 1.25V and a falling threshold of 1.125V. A startup delay of 220ms allows contacts and voltages to settle prior to initiating the startup sequence (Figure 12a).
CIRCUIT-BREAKER TRIP REGION
VCB VCB,MIN
CIRCUIT-BREAKER TRIP REGION VCB
VOLTAGE
VOLTAGE
ID x RDS,ON
ID x RDS,ON
RDS(ON) HIGH TEMPCO
VCB,MIN
RDS(ON) LOW TEMPCO
TA = +25C
TEMPERATURE
TA = +25C
TEMPERATURE
Figure 10. Circuit-Breaker Voltage Margin for High and Low Tempco Power MOSFETS 12 ______________________________________________________________________________________
-48V Hot-Swap Controllers with VIN Step Immunity and No RSENSE
This startup delay is from a valid UVLO condition until the start of the load-probe test. There is glitch rejection on UVLO going low, which requires that V UVLO remains below its falling threshold for 1.5ms to turn off the part (Figure 12b). Use the following formula to calculate the MAX5936/MAX59337 turn-on voltage: VON R2 = - 1 x R1 VUVLO_REF, R Where V ON is the desired turn-on voltage of the MAX5936/MAX5937 and V UVLO_REF,R is the 1.25V UVLO rising threshold.
Output Voltage (VOUT) Slew-Rate Control
The VOUT slew rate controls the inrush current required to charge the load capacitor. The MAX5936/MAX5937 have a default internal slew rate set for 9V/ms. The internal circuit establishing this slew rate accommodates up to about 1000pF of reverse transfer capacitance (miller capacitance) in the external power MOSFET without effecting the default slew rate. Using the default slew rate, the inrush current required to charge the load capacitance is given by: IINRUSH (mA) = CLOAD (F) x SR (V/ms) where SR = 9V/ms (default, typ).
MAX5936/MAX5937
Applications Information
VIN = (GND - VEE) GND R2
Selecting Resistor and Capacitor for Step Monitor
When a positive V IN step or ramp occurs, the V IN increase results in a voltage rise at both STEP_MON and V OUT relative to V EE . When the voltage at STEP_MON is above STEPTH the MAX5936/MAX5937 block short-circuit and circuit-breaker faults. During this STEP_MON high condition, if VOUT rises above VSC, the MAX5936/MAX5937 immediately and very rapidly pull GATE to VEE. This turns off the power MOSFET to avoid inrush current spiking. GATE is held low for 350s. About 1ms after the start of GATE pulldown, the MAX5936/MAX5937 begin to ramp GATE up to turn on the MOSFET in a controlled manner, which results in ramping VOUT down to the new supply level (see the GATE Cycles section in Appendix A).
MAX5936 MAX5937
UVLO
R1 VEE
Figure 11. Setting the MAX5936/MAX5937 Turn-On Voltage
UVLO
1.5ms
VUVLO_REF,F GATE VUVLO_REF,R UVLO 160ms ISC_DET LOAD PROBE DETECTION TEST BEGINS
VOUT PGOOD
(a)
(b)
Figure 12. UVLO Timing Diagram ______________________________________________________________________________________ 13
-48V Hot-Swap Controllers with VIN Step Immunity and No RSENSE MAX5936/MAX5937
This occurs with the least possible disturbance to VOUT, although during the brief period that the MOSFET is off, the voltage across the load droops slightly depending on the load current and load storage capacitance. PGOOD remains asserted throughout the V IN step event. The objective in selecting the resistor and capacitor for the step monitor function is to ensure that the VIN steps of all anticipated slopes and magnitudes will be properly detected and blocked, which otherwise would result in a circuit-breaker or short-circuit fault. The following is a brief analysis for finding the resistor and capacitor. For a more complete analysis, see Appendix B. Figure 13 is a functional diagram exhibiting the elements of the MAX5936/MAX5937 involved in the step immunity function. This block diagram shows the parallel relationship between VOUT and VSTEP-MON. Each has an I*R component establishing the DC level prior to a step. While it is referred to as a VIN step, it is the dynamic response to a finite voltage ramp that is of interest. Given a positive VIN ramp with a ramp rate of dV/dt, the approximate response of VOUT to VIN is: VOUT(t) = (dV/dt) x C x (1-e(-t / L,eqv) ) + RDS(ON) x ILOAD where C = CLOAD x RDS(ON) and L,eqv is the equivalent time constant of the load that must be found empirically (see Appendix B). Similarly, the response of STEP_MON to a VIN ramp is: VSTEP_MON(t) = (dV/dt) x STEP x (1-e(-t / STEP) ) + 10A x RSTEP where STEP = RSTEP_MON x CSTEP_MON. For proper step detection, V STEP_MON must exceed STEPTH prior to VOUT reaching VSC or within 1.4ms of VOUT reaching VCB (overall VIN ramp rates anticipated in the application). VSTEP_MON must be set below STEPTH with adequate margin, VSTEP_MON, to accommodate the tolerance of both ISTEP_OS (8%) and RSTEP_MON. R STEP_MON is typically set to 100k which gives a VSTEP_MON for a worst-case high of 0.36V.
GND CSTEP_MON
MAX5936 MAX5937
ISTEP_OS STEP_MON ISTEP STEPTH STEP_DET
FAULT MANAGEMENT
VSTEP_MON
CYCLE GATE LOW CLOAD
ESL
VIN STEP VSC SC TRIP
LOAD ESR
C RSTEP_MON
tCB_DLY VCB VEE GATE VOUT
CB TRIP
RDS,ON NOTE: VSC, VCB, VSTEPTH, VSTEP_MON, AND VOUT ARE REFERENCED TO VEE.
Figure 13. MAX5936/MAX5937 Step Immunity Functional Diagram 14 ______________________________________________________________________________________
-48V Hot-Swap Controllers with VIN Step Immunity and No RSENSE
The margin of VOUT with respect to VSC and VCB was set when VSC and VCB were selected from the three available ranges. This margin may be lower at one of the temperature extremes and if so, that value should be used in the following discussion. These margins will be called VCB and VSC and they represent the minimum VOUT excursion required to trip the respective fault. To set STEP to block all VCB and VSC faults for any ramp rate, find the ratio of VSTEP_MON to VCB and choose STEP so: STEP = 1.2 x C x VSTEP_MON / VCB And since R STEP_MON = 100k. This results in CSTEP_MON = STEP / 100k. After the first-pass component selection, if sufficient timing margin exists (see Appendix B), it is possible but not necessary to lower R STEP_MON below 100k to reduce the sensitivity of STEP_MON to VIN noise. Appendix B gives a more complete analysis and discussion of the step monitor function. It provides methods for the characterization of the load response to a VIN ramp and graphical verification of the step monitor timing margins for a set of design parameters. current is on, the load is assumed to be shorted and the current to the load from the LP pin is shut off. The MAX5936A_/MAX5937A_ time out for 16 x tLP then retry the load-probe test. The MAX5936L_/MAX5937L_ latch the fault condition indefinitely until the UVLO is brought below 1.125V for 1.5ms or the power is recycled. In the application, the current-limiting resistor should be selected to minimize the current pulled through the load while guaranteeing that it charges the maximum expected load capacitance to 220mV in 80ms. These parameters are the maximum load-probe test voltage and the minimum load-probe current pulse period, respectively. The maximum current possible is 1A, which is adequate to test a load capacitance as large as 170,000F over the typical telecom operating voltage range. ITEST (A) = CLOAD,MAX (F) x 220mV / 80ms Since the minimum intended V IN for the application results in the lowest ITEST, during the load-probe test, this VIN,MIN should be used to set the RLP. This voltage will likely be near VON,FALLING or VOFF for the application. RTEST() = VIN,MIN / ITEST = VIN,MIN x 80ms / (CLOAD(MAX) x 220mV) Example: VIN operating range = 36V to 72V, CLOAD = 10,000F. First, find the RTEST, which will guarantee a successful test of the load. RLP = 36V x 80ms / (10,000F x 220mV) = 1,309 1.30k 1% Next, evaluate the RLP at the maximum operating voltage to verify that it will not exceed the 1A current limit for the load-probe test: ITEST,MAX = VIN,MAX / RLP = 72V / 1.30k = 55.4mA If the CLOAD(MAX) is increased to 170,000F, the test current will approach the limit. In this case, RTEST will be a much lower value and must include the internal switch resistance. To find the external series resistor value that will guarantee a successful test at the lowest supply voltage, the maximum value for the load-probe switch on-resistance of 11 should be used: RLP,TOT = 36V x 80ms / (170,000F x 220mV) = 77 = 11 + RLP RLP = 77 - 11 = 66 66.5 1% Again RLP must be evaluated at the maximum operating voltage to verify that it will not exceed the 1A current limit for the load-probe test. In this case, the minimum value for the load-probe switch on-resistance of 6 should be used: ITEST,MAX = VIN,MAX / RLP,TOT = 72V / (66.5 + 6) = 993mA
15
MAX5936/MAX5937
Selecting the PGOOD (PGOOD) Pullup Resistor
Due to the open-drain driver, PGOOD (PGOOD) requires an external pullup resistor to GND. This resistor should be selected to minimize the current load while PGOOD (PGOOD) is low. The PGOOD output specification for VOL is 0.4V at 1mA. As described in the Detailed Description, the external pullup interferes with the ability of PGOOD (PGOOD) to follow positive VIN steps as well as if it were driven by an active pullup. When PGOOD (PGOOD) is asserted high, an apparent negative glitch appears at PGOOD during a positive VIN step. To minimize this negative transient it may be necessary to increase the pullup current and/or to add a small amount of capacitance from PGOOD (PGOOD) to GND to compensate for the pin capacitance.
Setting the Test Current Level for Load-Probe Test
The load-probe test is a current test of the load that avoids turning on the power MOSFET. The MAX5936/ MAX5937 have an internal switch (Q1 in Figure 14) that pulls current through the load and through an external current-limiting resistor, RLP. During the test, this switch is pulsed on for up to 220ms (typ). Current is pulled through the load, which should charge up the load capacitance unless there is a short. If the voltage across the load exceeds 200mV, the test is truncated and normal powerup is allowed to proceed. If the voltage across the load does not reach 200mV in the 220ms period that the
______________________________________________________________________________________
-48V Hot-Swap Controllers with VIN Step Immunity and No RSENSE MAX5936/MAX5937
GND
200mV
MAX5936 MAX5937
LOAD OK
VIN
TIMING LOGIC Q1
ILOAD VEE GATE VOUT ITEST RLP CLOAD LOAD
RON
Figure 14. Load Probe Functional Diagram
Adjusting the VOUT Slew Rate The default slew rate is set internally for 9V/ms. The slew rate can be reduced by placing an external capacitor from the drain of the power MOSFET to the GATE output of the MAX5936/MAX5937. Figure 15 shows a graph of Slew Rate vs. CSLEW. This graph shows that for CSLEW < 4700pF there is very little effect to the addition of external slew-rate control capacitance. This is intended so the GATE output can drive large MOSFETs with significant gate capacitance and still achieve the default slew rate. To select a slew-rate control capacitor, go into the graph with the desired slew rate and find the value of the miller capacitance. When CSLEW > 4700pF, SR and CSLEW are inversely related. Given the desired slew rate, the required CSLEW is found as follows: CSLEW(nF) = 23 / SR (V/ms) From the data sheet of the power MOSFET find the reverse transfer capacitance (gate-to-drain capacitance) above 10V. If the reverse transfer capacitance of the external power MOSFET is 5% or more of CSLEW, then it should be subtracted from CSLEW in the equation above.
Figure 16 gives an example of the external circuit for controlling slew rate. Depending on the parasitics asso-
ciated with the selected power MOSFET, the addition of CSLEW may lead to oscillation while the MOSFET and GATE control are in the linear range. If this is an issue, an external resistor, RGATE, in series with the gate of the MOSFET is recommended to prevent possible oscillation. It should be as small as possible, e.g., 5 to 10, to avoid impacting the MOSFET turn-off performance of the MAX5936/MAX5937.
Layout Guidelines
To benefit from the temperature compensation designed into the MAX5936/MAX5937, the part should be placed as close as possible to the power MOSFET that it is controlling. The VEE pin of the MAX5936/ MAX5937 should be placed close to the source pin of the power MOSFET and they should share a wide trace. A common top layer plane would service both the thermal and electrical requirements. The load-probe current must be taken into account. If this current is high, the layout traces and current-limiting resistor must be sized appropriately. Stray inductance must be minimized in the traces of the overall layout of the hot-swap controller, the power MOSFET, and the load capacitor. Starting from the board contacts, all high-current traces should be short, wide, and direct. The potentially high pulse current pins of the MAX5936/MAX5937 are GATE (when pulling GATE low),
16
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-48V Hot-Swap Controllers with VIN Step Immunity and No RSENSE
Input Transient Protection
SLEW RATE vs. CSLEW
10
MAX5936/MAX5937
1
0.1
During hot plug-in/unplug and fast VIN steps, stray inductance in the power path can cause voltage ringing above the normal input DC value, which may exceed the absolute maximum supply rating. An input transient such as that caused by lightning can also put a severe transient peak voltage on the input rail. The following techniques are recommended to reduce the effect of transients: 1) Minimize stray inductance in the power path using wide traces and minimize loop area including the power traces and the return ground path.
1000
SLEW RATE (V/ms)
0.01 0.1 1 10 CSLEW (nF) 100
2) Add a high-frequency (ceramic) bypass capacitor on the backplane as close as possible to the plugin connector (Figure 17). 3) Add a 1k resistor in series with the MAX5936/ MAX5937's GND pin and a 0.1F capacitor from GND to VEE to limit transient current going into this pin.
Figure 15. MAX5936/MAX5937 Slew Rate vs. CSLEW
Appendix A
GND GND CLOAD LOAD
GATE Cycles
The power-up GATE cycle and the step GATE cycle are quite similar but have distinct differences. Understanding these differences may clarify application issues. GATE Cycle During Power-Up The power-up GATE cycle occurs during the initial power-up of the MAX5936/MAX5937 and the associated power MOSFET and load. The power-up GATE cycle can result in full enhancement or in a fault (all voltages are relative to VEE). Power-Up to Full Enhancement:
CSLEW
MAX5936 MAX5937
VOUT
VEE
GATE
RGATE
-48V
1) At the beginning of the power-up sequence to the start of the power-up GATE cycle, the GATE is held at VEE. Following a successful completion of the load-probe test, GATE is held at VEE for an additional 350s and then is allowed to float for 650s. At this point, the GATE begins to ramp with 52A charging the gate of the power MOSFET. [GATE turn-on] 2) When GATE reaches the gate threshold voltage of the power MOSFET, VOUT begins to ramp down toward VEE. [VOUT ramp] 3) When VOUT ramps below 72% VCB, the GATE is rapidly pulled to full enhancement and the powerup GATE cycle is complete. 1.26ms after GATE is pulled to full enhancement, PGOOD will assert. [Full enhancement]
Figure 16. Adjusting the MAX5936/MAX5937 Slew Rate
load-probe, and VEE. Because of the nature of the hotswap requirement, no decoupling capacitor is recommended for the MAX5936/MAX5937. Because there is no decoupling capacitor, stray inductance can result in excessive ringing at the GND pin during power-up or during very rapid VIN steps. This should be examined in every application design since ringing at the GND pin may exceed the absolute maximum supply rating for the part.
______________________________________________________________________________________
17
-48V Hot-Swap Controllers with VIN Step Immunity and No RSENSE MAX5936/MAX5937
BACKPLANE 48V 10% PLUG-IN CARD
begins to ramp with 52A charging the gate of the power MOSFET. [GATE turn-on] 4) When GATE reaches the gate threshold voltage of the power MOSFET, VOUT begins to ramp down toward the new lower VEE. In the interval where GATE is below the MOSFET threshold, the MOSFET is off and VOUT will droop depending on the RC time constant of the load. [VOUT ramp] 5) When VOUT ramps below 72% VCB, the GATE pulls rapidly to full enhancement and the step GATE cycle is complete. If STEP_MON remains above STEP TH when GATE has ramped to 90% of full enhancement and V OUT remains above 72% of VCB, GATE remains at 90% and will not be pulled to full enhancement. In this condition, if VOUT drops below 72% of VCB before STEP_MON drops below STEPTH, GATE is rapidly pulled to full enhancement and the step GATE cycle is complete. PGOOD remains asserted throughout the step GATE cycle. [Full enhancement] Step to Fault Management: 1) Same as step 1 above. [Step detection] 2) Same as step 2 above. [GATE pulldown] 3) Same as step 3 above. [GATE turn-on] 4) Same as step 4 above. [VOUT ramp] 5) If STEP_MON is below STEPTH when GATE ramps to 90% of full enhancement and V OUT remains above 72% V CB, GATE is rapidly pulled to V EE. Fault management is initiated and PGOOD is deasserted. If STEP_MON is above STEP TH when GATE ramps to 90% of full enhancement and VOUT remains above 72% of VCB, GATE remains at 90%. It will not be pulled to full enhancement nor will it be pulled to VEE. In this condition, if VOUT drops below 72% of V CB before STEP_MON drops below STEPTH, GATE is rapidly pulled to full enhancement and a fault is avoided. Conversely, if STEP_MON drops below STEP TH first, the GATE is rapidly pulled to VEE, fault management is initiated, and PGOOD is deasserted. [Fault management] It should be emphasized that while STEP_MON remains above STEP TH the current fault management is blocked. During this time it is possible for there to be multiple events involving VOUT rising above VSC then those falling below 75% VCB. In each of these events, when VOUT rises above VSC, a full GATE cycle is initiated where GATE is first pulled low then allowed to ramp up. Then finally, when VOUT conditions are met, it will be fully enhanced.
1k 100k
GND 1F 0.1F 68V TVS PGOOD
VEE
Figure 17. Protecting the MAX5936/MAX5937 Input from HighVoltage Transients
Power-Up to Fault Management: 1) Same as step 1 above. [GATE turn-on] 2) Same as step 2 above. [VOUT ramp] 3) GATE ramps to 90% of full enhancement while VOUT remains above 72% VCB, at which point the GATE is rapidly pulled to VEE and fault management is initiated. [Fault management] GATE Cycle During VIN Step A step GATE cycle occurs only after a successful power-up GATE cycle to full enhancement occurs and as a result of a positive V IN step (all voltages are relative to VEE). Step to Full Enhancement: 1) A VIN step occurs resulting in STEP_MON rising above STEPTH before VOUT rises above VSC. [Step detection] 2) After a step is detected, VOUT rises above VSC in response to the step. When VOUT rises above VSC, GATE is immediately pulled to VEE, rapidly turning off the power MOSFET. GATE is held at VEE for 350s to dampen any ringing. Once GATE is pulled to VEE, the gate cycle has begun and STEP_MON can safely drop below STEPTH and successfully complete a step GATE cycle to full enhancement without initiating fault management. [GATE pulldown] 3) Following the 350s of GATE pulldown, GATE is allowed to float for 650s. At this point, the GATE
18
______________________________________________________________________________________
-48V Hot-Swap Controllers with VIN Step Immunity and No RSENSE
GATE Output
GATE is a complex output structure and its condition at any moment is dependent on various timing sequences in response to multiple inputs. A diode to VEE prevents negative excursions. For positive excursions, the states are: 1) Power-off with 2V clamp. 2) 10 pulldown to VEE. a. Continuous during startup delay and during fault conditions. b. Pulsed following detected step or OV condition. 3) Floating with 15V clamp. [Prior to GATE ramp] 4) 47A current source with 15V clamp. [GATE ramp] 5) Pullup to internal 10V supply with 15V clamp. [Full enhancement] Similarly, the response of STEP_MON to a VIN ramp is: VSTEP_MON(t) = (dV/dt) x STEP x (1-e(-t / STEP) ) + 10A x RSTEP_MON (Equation 2) where STEP = RSTEP_MON x CSTEP_MON. For proper step detection, V STEP_MON must exceed STEPTH prior to VOUT reaching VSC or within 1.4ms of VOUT reaching VCB (or overall VIN ramp rates anticipated in the application). It is impossible to give a fixed set of design guidelines that rigidly apply over the wide array of applications that use the MAX5936/ MAX5937. There are, however, limiting conditions and recommendations that should be observed. One limiting condition that must be observed is to ensure that the STEP_MON time constant, STEP, is not so low that at the lowest ramp rate, the anticipated STEPTH cannot be obtained. The product (dV/dt) x STEP = STEP_MON,MAX, is the maximum differential voltage at STEP_MON if the VIN ramp were to continue indefinitely. A related condition is setting the STEP_MON voltage below STEPTH with adequate margin, VSTEP_MON, to accommodate the tolerance of both ISTEP_OS (8%) and RSTEP_MON. In determining STEP_MON, use the 9.2A limit to ensure sufficient margin with worst-case ISTEP_OS. The margin of VOUT (with respect to VSC and VCB) is set when VSC and VCB were selected from the three available ranges. This margin may be lower at one of the temperature extremes and if so, that value should be used in the following discussion. These margins will be called VCB and VSC and they represent the minimum VOUT excursion required to trip the respective fault. RSTEP_MON is typically set to 100k 1%. This gives a V STEP_MON of 0.25V, a worst-case low of 0.16V, and a worst-case high of 0.37V. In finding STEP in the equation below, use V STEP_MON = 0.37V to ensure sufficient margin with worst-case ISTEP_OS. To set STEP to block all VCB and VSC faults for any ramp rate, find the ratio of VSTEP_MON to VCB and choose STEP so: STEP = 1.2 x C x VSTEP_MON / VCB and since RSTEP_MON = 100k: CSTEP_MON = STEP / RSTEP_MON = STEP / 100k After the first-pass component selection, if sufficient timing margin exists, it is possible but not necessary to lower RSTEP below 100k to reduce the sensitivity of STEP_MON to VIN noise.
MAX5936/MAX5937
Appendix B
Step Monitor Component Selection Analysis
As mentioned previously in the Selecting Resistor and Capacitor for Step Monitor section, the AC response from VIN to VOUT is dependent on the parasitics of the load. This is especially true for the load capacitor in conjunction with the power MOSFET's R DS(ON). The load capacitor (with parasitic ESR and LSR) and the power MOSFET's RDS(ON) can be modeled as a heavily damped second-order system. As such, this system functions as a bandpass filter from VIN to VOUT limiting the ability of VOUT to follow the VIN ramp. STEP_MON lags the VIN ramp with a first-order RC response, while V OUT lags with an overdamped second-order response. Given a positive VIN ramp with ramp rate of dV/dt, the approximate response of VOUT to VIN is: VOUT(t) = (dV/dt) x C x (1-e(-t / L,eqv) ) + RDS(ON) x ILOAD (Equation 1) where C = CLOAD x RDS(ON). Equation 1 is a simplification for the overdamped second-order response of the load to a ramp input, C = CLOAD x RDS(ON), and corresponds to the ability of the load capacitor to transfer dV/dt current to the fully enhanced power MOSFET's RDS(ON). The equivalent time constant of the load (L,eqv) accounts for the parasitic series inductance and resistance of the capacitor and board interconnect. Determine L,eqv empirically with a few tests to characterize the load dynamic response to VIN ramps.
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19
-48V Hot-Swap Controllers with VIN Step Immunity and No RSENSE MAX5936/MAX5937
Verification of the Step Monitor Timing
It is prudent to verify conclusively that all circuit-breaker and short-circuit faults will be blocked for all ramp rates. To do this, some form of graphical analysis is recommended but first, find the value of L,eqv of the load by a series of ramp tests as indicated earlier. These tests include evaluating the load with a series of VIN ramps of increasing ramp rates and monitoring the rate of V OUT rise during the ramp. Each V IN ramp should have a constant slope. The VOUT response data must be taken only during the positive ramp. Data taken after VIN has leveled off at the new higher value must not be used. Figure 18 shows the load in parallel with the load capacitor, CLOAD, and the parallel connection in series with the power MOSFET, which is fully enhanced with VGS = 10V. The objective is to determine L,eqv from the VOUT response. Figure 19 shows the general response of VOUT to a VIN ramp over time t. Equation 1 gives the response of VOUT to a ramp of dV/dt. The product (dV/dt) x C = VOUT(max) or the maximum VOUT voltage differential if the VIN ramp were to continue indefinitely. The parameter of interest is VOUT due to the ramp dV/dt, thus it is necessary to subtract the DC shift in VOUT due to the load resistance. For some loads, which are relatively independent of supply voltage, this may be insignificant. VOUT(t) = VOUT(t) - RDS(ON) x ILOAD where ILOAD is a function of the VOUT level that should be determined separately with DC tests. At any time (t) the VOUT fraction of VOUT(max) is: VOUT(t) / [(dV/dt) x C] = (1-e(-t / L,eqv)) If VOUT(t) is measured at time t, then the equivalent time constant of the load is found from: L,eqv = -t / ln(1 - VOUT / [(dV/dt) x C]) As mentioned earlier, several measurements of VOUT at times t1, t2, t3, and t4 should be made during the ramp. Each of these may result in slightly different values of L,eqv and all values should then be averaged. In making the measurements, the VIN ramp duration should be such that VOUT reaches 2 or 3 times the selected VSC. The ramp tests should include three ramp rates: VSC / C, 2 x VSC / C and 4 x VSC / C. The values of L,eqv may vary over the range of slew rates due to measurement error, nonlinear dynamics in the load, and due to the fact that Equation 1 is a simplification from a higher order dynamic system. The resulting range of L,eqv values should be used to validate the performance of the final design. Having C, L,eqv, RSTEP, and CSTEP in a graphical analysis using Equation 1 and Equation 2 can verify the step monitor function by displaying the relative timing of tCB, tSTEP, and tSC, which are the times when VCB, VSTEP_MON, and VSC voltage thresholds are exceeded. A simple spreadsheet for this purpose can be supplied by Maxim upon request. Figures 20, 21, and 22 graphically verify a particular solution over 3 decades of VIN ramp rates. In addition, Figure 22 verifies that this solution will block all circuit-breaker and short-circuit faults for even the lowest VIN ramp that will cause VOUT to exceed VCB.
VIN LEQU LOAD CAPACITOR WITH PARASITICS REQV VOUT.F 10V CLOAD VOUTi 0 VIN RAMP RDS,ON t1 t2 t3 t4 dv C dt dv dt LOAD
VIN RAMP
Figure 18. VIN Ramp Test of Load 20 ___________________________________________________
Figure 19. General Response of VOUT to a VIN Ramp
-48V Hot-Swap Controllers with VIN Step Immunity and No RSENSE MAX5936/MAX5937
VOUT RESPONSE TO VIN RAMP OF 300V/ms
2.7 2.4 2.1 VOLTAGES (V) 1.8 1.5 1.2 0.9 0.6 0.3 0 0 1 2 3 4 TIME (s) A = VIN (GND - VEE) B = VSTEP_MON C = VOUT D = VSTEP,TH E = VCB F = VSC A = VIN (GND - VEE) B = VSTEP_MON C = VOUT 5 6 7 8 tCB tSTEP C tSC E F 0.2 0 0 4 8 12 16 20 24 28 32 36 40 TIME (s) D = VSTEP,TH E = VCB F = VSC dVIN dt A B VOLTAGES (V) 1.4 1.2 A 1.0 0.8 0.6 0.4 tCB F E tSTEP B
VOUT RESPONSE TO VIN RAMP
D C tSC
Figure 20. VOUT Response to VIN Ramp of 300V/ms
Figure 21. VOUT Response to VIN Ramp of 30V/ms
Chip Information
TRANSISTOR COUNT: 2320 PROCESS: BiCMOS
VOUT RESPONSE TO VIN RAMP OF 3V/ms
1.6 1.4 1.2 VOLTAGES (V) 1.0 0.8 0.6 0.4 0.2 C 0 0 100 200 300 400 500 TIME (s) A = VIN (GND - VEE) B = VSTEP_MON C = VOUT D = VSTEP,TH E = VCB F = VSC F E D tSTEP B A
Figure 22. VOUT Response to VIN Ramp of 3V/ms
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21
-48V Hot-Swap Controllers with VIN Step Immunity and No RSENSE MAX5936/MAX5937
Timing Table
NAME Power-Up Delay Load Probe Test Timeout Load Probe Retry Time PGOOD (PGOOD) Assertion Delay Time Autoretry Delay Circuit-Breaker Glitch Rejection UVLO Glitch Rejection GATE Pulldown Pulse Following a VIN step GATE Low After a VIN Step, Prior to Ramp SYMBOL tONDLY tLP tLP_OFF tPGOOD tRETRY tCB_DLY tREJ -- -- TYPICAL TIME (s) 220m 220m 3.5 1.26m 3.5 1.4m 1.5m 350 1m MAX5936LA MAX5936LB MAX5936LC MAX5936LN MAX5936AA MAX5936AB MAX5936AC MAX5937LA MAX5937LB MAX5937LC MAX5937LN MAX5937AA MAX5937AB MAX5937AC PART
Selector Guide
CIRCUITPGOOD FAULT BREAKER THRESHOLD MANAGEMENT ASSERTION (mV) 100 200 400 No circuit breaker 100 200 400 100 200 400 No circuit breaker 100 200 400 Latch Latch Latch Latch Autoretry Autoretry Autoretry Latch Latch Latch Latch Autoretry Autoretry Autoretry Low Low Low Low Low Low Low High High High High High High High
Typical Operating Circuit
GND GND * V+ DC-DC CONVERTER
CLOAD
MAX5937
UVLO *
PGOOD
ON V-
VOUT
BACKPLANE
VIN
STEP_MON
LP
VEE
GATE * *
-48V *OPTIONAL COMPONENTS
22
______________________________________________________________________________________
-48V Hot-Swap Controllers with VIN Step Immunity and No RSENSE
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
MAX5936/MAX5937
INCHES DIM A A1 B C e E H L MAX MIN 0.069 0.053 0.010 0.004 0.014 0.019 0.007 0.010 0.050 BSC 0.150 0.157 0.228 0.244 0.016 0.050
MILLIMETERS MAX MIN 1.35 1.75 0.10 0.25 0.35 0.49 0.19 0.25 1.27 BSC 3.80 4.00 5.80 6.20 0.40 1.27
N
E
H
VARIATIONS:
1
INCHES
MILLIMETERS MIN 4.80 8.55 9.80 MAX 5.00 8.75 10.00 N MS012 8 AA 14 AB 16 AC
TOP VIEW
DIM D D D
MIN 0.189 0.337 0.386
MAX 0.197 0.344 0.394
D C
A e B A1
0 -8 L
FRONT VIEW
SIDE VIEW
PROPRIETARY INFORMATION TITLE:
PACKAGE OUTLINE, .150" SOIC
APPROVAL DOCUMENT CONTROL NO. REV.
21-0041
B
1 1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 23 (c) 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.
SOICN .EPS

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